1. Technical Field
The present invention relates to an FSK (Frequency Shift Keying) receiver. More particularly, the present invention relates to an FSK demodulator of an FSK receiver.
2. Description of the Related Art
In general, as shown in FIG. 1, an FSK demodulator constituting a FSK receiver according to the related art includes a frequency detector 11, a frequency offset cancellation circuit 12, and a symbol timing regenerator 13. The frequency detector 11 converts frequency shift information of an FSK-modulated wave of a received IF signal into an amplitude value to generate a frequency detection signal. The frequency offset cancellation circuit 12 cancels frequency offset components, which are generated due to frequency errors between local oscillators of a transmitter and a receiver, from the frequency detection signal. The symbol timing regenerator 13 generates the optimal symbol timing based on a detection signal and performs data decision based on a detection signal obtained after the frequency offset components have been cancelled from the frequency detection signal.
According to one scheme to realize the frequency offset cancellation circuit 12, frequency offset components are calculated by extracting points (inflection points), at which the second derivative of a frequency detection waveform is zero, from the frequency detection waveform, and averaging the points (see Patent Literature 1).
When the frequency offset cancellation circuit 12 employs the above scheme of extracting the inflection points, the frequency offset cancellation circuit 12 may include, for example, an inflection point detector 21, an averaging circuit 22, and a subtraction circuit 23 as shown in FIG. 2. The inflection point detector 21 receives a frequency detection signal S0 which is an output signal of the frequency detector 11 to generate inflection point timings of the frequency detection signal S0. The averaging circuit 22 averages amplitude values of the inflection point timings which are output from the inflection point detector 21. The subtraction circuit 23 subtracts the average amplitude information (frequency offset signal) of the inflection point timings, which is an output signal of the averaging circuit 22, from the output signal of the frequency detector 11 to generate a frequency detection signal after the frequency offset components are canceled.
For example, the inflection point detector 21 has a structure shown in FIG. 3. The inflection point detector 21 of FIG. 3 has a circuit structure of detecting inflection points at an operating clock rate which is 16 times greater than a symbol rate. The inflection point detector 21 includes a 16-stage shift register 31 to store sample values corresponding to amplitude values of the frequency detection signal S0 for one symbol after sampling the frequency detection signal S0 according to the operating clock, a subtracter C1 to subtract a first output of the 16-stage shift register 31 from an eighth output of the 16-stage shift register 31, a subtracter C2 to subtract a ninth output of the 16-stage shift register 31 from a 16th output of the 16-stage shift register 31, a subtracter C3 to perform subtraction with respect to outputs of the subtracters C1 and C2, a subtracter C4 to subtract the first output of the 16-stage shift register 31 from the 16th output of the 16-stage shift register 31, an absolute value circuit C5 to calculate an absolute value of an output of the subtracter C3, an absolute value circuit C6 to calculate an absolute value of an output of the subtracter C4, a comparator C7 to compare an output value of the absolute value circuit C5 with threshold values A and B in size, a comparator C8 to compare an output value of the absolute value circuit C6 with a threshold value C in size, an AND circuit C9 to perform an AND operation with respect to outputs of the comparators C7 and C8, an edge detector C10 to detect the rising edge of an output of the AND circuit C9, and a pre-frequency offset generator C11 to extract a frequency detection value at the inflection point timing from an inflection point timing signal, which is an output of the edge detector C10, and the output signal of the frequency detector 11. In addition, the subtracters C1 to C3, the absolute value circuit C6, and the comparator C8 constitute an inflection point extraction circuit 32, and the subtracter C4, the absolute value circuit C5, and the comparator C7 constitute an amplitude monitoring circuit 33.
In the inflection point detector 21 having the above structure, the levels of the input frequency detection signal S0 are shifted from a first shift register to a 16th shift register one by one in synchronization with the operating clock of the 16-shift register 31 while the levels of the input frequency detection signal S0 are being retained in the 16-stage shift register 31. In this case, the first output to the 16th output of the 16-stage shift register 31 for the frequency detection signal S0 having the waveform of FIG. 4 have signal levels as shown in FIG. 4. In the inflection point extraction circuit 32, an operation result S1 of the subtracter C1 and an operation result S2 of the subtracter C2 are obtained as “b−a” and “d−c”, and the gradient of the frequency detection signal S0 at the duration corresponding to 8 operating clock pulses is calculated at each operating clock. In addition, the difference of the differential values (i.e., S2−S1=(d−c)−(b−a)) is made by the subtracter C3, and the absolute value (|(d−c)−(b−a)|) of the difference is calculated by the absolute value circuit C6. Since the difference of two differential values S2 and S1 correspond to the value of a second derivative, a point having a value less than or equal to the threshold C is regarded as an inflection point. Therefore, the inflection point can be obtained from the comparator C8.
In addition, in order to prevent inflection points from being erroneously detected due to noise, the amplitude monitoring circuit 33 is provided. The amplitude monitoring circuit 33 regards an amplitude S3 of the frequency detection signal S0 of the received IF signal as noise if the amplitude S3 (value between peaks) of the frequency detection signal S0 is greater than or equal to the threshold value A, or less than or equal to the threshold value B. An output representing the presence of noise is obtained from the comparator C7.
The AND circuit C9 negates an inflection point if the inflection point is detected by the inflection point extraction circuit 32 at the timing in which the amplitude S3 of the frequency detection signal S0 is regarded as noise due to the condition of S3≧A or S3≦CB. Meanwhile, the AND circuit C9 outputs an inflection point if the inflection point is detected by the inflection point extraction circuit 32 in the state that a condition of B<S3<A is satisfied.
An inflection point timing signal S4 is obtained by detecting the rising edge of the output of the AND circuit C9 in the edge detector C10. In addition, the pre-frequency offset generator C11 extracts the center value of the frequency detection signal S0 from the inflection point timing signal S4 and generates a pre-frequency offset signal by using the center value. A final frequency offset signal representing offset components is calculated by performing an averaging operation with respect to the pre-frequency offset signal by the averaging circuit 22 provided at a next stage.
Patent Literature 1: Japanese Patent Kokai No. 2006-325127